1. Field of the Invention
This invention relates to a circuit counter of an output comparing type.
2. Description of the Related Art
FIG. 1 is a block diagram showing the structure of a conventional output-comparing type counter circuit. In the counter circuit of FIG. 1, clocks CLK to be counted are inputted to a counter 1. Data is sent and received between the counter 1 and a bus BS. The counted value by the counter 1 and the set value of a comparison register 2 are fed to a comparator 3. A comparison signal CS outputted from the comparator 3 is sent to a gate terminal of a transfer gate TG1. When the transfer gate TG1 is closed upon receipt of the comparison signal CS, the value of a latch circuit 4 is given to a latch circuit 5 via the transfer gate TG1, whereby the latch circuit 5 outputs the value.
Write signals WT1, WT2 are sent to the gate terminals of a transfer gates TG2, TG3 respectively. In consequence, as the transfer gates TG2, TG3 are turned in the operable state, the data of the bus BS is transferred to the comparison register 2 via the transfer gate TG2 and to the latch circuit 4 via the transfer gate TG3, respectively.
The operation of the above-constructed conventional counter circuit will be depicted now.
The counter 1 continues to count up the clocks after it is enabled. In the first place, the counted value of the counter 1 which corresponds to the timing whereby the output value of the counter circuit is to be changed is set to the comparison register 2, and a target output value is set to the latch circuit 4. When the counted value of the counter 1 is detected to have reached the set value of the comparison register 2, the comparator 3 generates a comparison signal CS. Synchronously with this comparison signal CS, the transfer gate TG1 becomes operable, and the value of the latch circuit 4 is transferred to the latch circuit 5, and the value fed to the latch circuit 5 is outputted from the latch circuit 5, thereby to change the output value of the counter circuit.
In the manner as above, since the set value of the comparison register 2 corresponding to the timing whereby the output value of the counter circuit is to be changed and the set output value of the latch circuit 4 are sequentially changed, it enables the counter circuit to output the waveform of a desired time width. In order to change the set value of the comparison register 2, after a CPU (not shown) calculates a changed-to-be value, the CPU reads the current counted value of the counter 1, compares the counted value with the set value of the comparison register 2 to judge whether or not it is a changeable timing. Only when the timing is judged to be changeable, the value of the comparison register 2 is changed.
FIG. 2 is a diagram showing the change of the counted value of the counter 1 and the output value of the counter circuit. If the output waveform indicated in FIG. 2(b) is required, an "H" value is set to the latch circuit 4, an "L" value is set to the latch circuit 5 and the value at a time point t1 is set to the comparison register 2, when the counter 1 is activated. The counted value of the counter 1 increases as shown in FIG. 2(a). At the time point T1 when the counted value of the counter 1 becomes the value of the comparison register 2, the comparator 3 generates the comparison signal CS and the "H" value of the latch circuit 4 is transferred to the latch circuit 5. Accordingly, as the value of the latch circuit 5 is changed from "L" to "H", the output waveform of the counter circuit rises as represented by a solid line in FIG. 2(b).
Corresponding to the generation of the comparison signal CS, and "L" value and the value at a time point t2 are set respectively to the latch circuit 4 and the comparison register 2, for example, at the occurrence of an interruption or the like. Thereafter, at the time point t2 when the counted value of the counter 1 reaches the value of the comparison register 2 again, the comparator 3 outputs the comparison signal CS, and the "L" value of the latch circuit 4 is transferred to the latch circuit 5. Since the value of the latch circuit 5 is changed from "H" to "L", the output waveform of the counter circuit falls as indicated by the solid line of FIG. 2(b). Subsequently, in accordance with the output of the comparison signal CS and consequent to the generation of an interruption or the like, an "H" value is set to the latch circuit 4 and the value of the next rise timing is set to the comparison register 2. The waveform of FIG. 2(b) is repeatedly obtained when the above sequence of control is repeated.
When the set value of the comparison register 2 is desired to be changed, as described above, the current counted value of the counter 1 should be read out after the changed-to-be value is calculated by the CPU, and the counted value should be compared with the set value of the comparison register 2 thereby to judge whether it is the timing able to be changed. Therefore, although it is enough to finish changing the output value of the counter circuit before the timing "B", the changed-to-be value should be completely calculated before the timing "A", as is clear from FIG. 2(b). In the case, for instance, where the counter circuit is used with an aim to control the engine, the time width "C" between the timings "A" and "B" which corresponds to the time required for the CPU to make a judgement is set considerably long, and therefore, the changed-to-be value cannot be calculated in time before the timing "A" even in need of the change. As a result, the value of the comparison register 2 is not changed in most cases.
Meanwhile, if the value of the comparison register 2 is arranged to be changed to a sufficiently larger value than the timing whereby it is expected that setting of the calculated change-to-be value to the comparison register 2 and the latch circuit 4 is completed, without making the CPU judge whether or not it is the changeable timing, any abnormal waveform is not particularly generated, and the waveform illustrated in FIG. 2(c) is obtained. If the comparison register 2 is changed to a smaller value, and if the timing whereby setting of the changed-to-be value is finished is the changeable timing prior to the set timing, the comparison signal CS is detected when the counted value of the counter 1 reaches the set value of the comparison register 2, so that the output waveform shown by a broken line is FIG. 2(d) which falls at a time point prior to the fall time point indicated by a solid line is obtained. On the other hand, however, if the timing whereby setting is finished is the timing subsequent to the set timing, the comparison signal CS is not obtained when the counter 1 assumes the changed-to-be value. As a result, as shown by a chain line in FIG. 2(d), the time width of the output waveform becomes abnormally long, without a fall.
As discussed hereinabove, when the once-set value of the comparison register is to be changed in the conventional counter circuit, it is necessary to judge by the CPU whether or not it is changeable before a changed-to-be value is calculated. Only a short time is left to finish the calculation of the changed-to-be value. It is impossible to calculate the changed-to-be value before time is up if a long time is allotted for the judgement by the CPU. The value of the comparison register cannot be eventually changed.